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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. AD8362 50 hz to 2.7 ghz 60 db trupwr detector features complete fully calibrated measurement/ control system accurate rms-to-dc conversion from 50 hz to 2.7 ghz input dynamic range of >60 db ?2 dbm to 8 dbm in 50 waveform and modulation independent (gsm/cdma/tdma, and so on) linear-in-decibels output, scaled 50 mv/db law conformance error of 0.5 db all functions temperature and supply stable operates from 4.5 v to 5.5 v at 24 ma from ?0 c to +85 c power-down capability to 1.3 mw applications power amplifier linearization/control loops transmitter power control transmitter signal strength indication (tssi) rf instrumentation functional block diagram bias x 2 v out vset pwdn comm vref AD8362 inhi inlo vtgt vpos clpf chpf x 2 a com decl general description the AD8362 is a true-rms-responding power detector having a 60 db measurement range. it is intended for use in a variety of high frequency communication systems, and in instrumentation requiring an accurate response to signal power. it is easy to use, requiring only a single supply of 5 v and a few capacitors. it can operate from arbitrarily low frequencies to over 2.7 ghz and can accept inputs that have rms values from 1 mv to at least 1 v rms, with peak crest factors of up to six, exceeding the require- ments for accurate measurement of cdma signals. the input signal is applied to a resistive ladder attenuator that comprises the input stage of a variable gain amplifier. the twelve tap points are smoothly interpolated using a proprietary technique to provide a continuously variable attenuator, which is controlled by a voltage applied to pin vset. the resulting signal is applied to a high performance broadband amplifier. its output is measured by an accurate square law detector cell. the fluctuating output is then filtered and compared with the output of an identical squarer, whose input is a fixed dc voltage applied to pin vtgt, usually the accurate reference of 1.25 v provided at pin vref. the difference in the outputs of these squaring cells is integrated in a high gain error amplifier, generating a voltage at pin vout with rail-to-rail capabilities. in a controller mode, this low noise output can be used to vary the gain of a host system? rf ampli- fier, thus balancing the set point against the input power. optionally, the voltage at vset may be a replica of the rf signal? amplitude modulation, in which case the overall effect is to remove the modulation component prior to detection and low pass filtering. the corner frequency of the averaging filter may be lowered without limit by the addi tion of an external capacitor at pin clpf, the AD8362 can be used to determine the true power of a high frequency signal having a complex low frequency modulation envelope ( or simply as a low frequency rms voltmeter). the high-pass corner generated by its offset- nulling loop can be lowered by a capacitor added on pin chpf. used as a power measurement device, pin vout is strapped to vset, and the output is then proportional to the logarithm of the rms value of the input; that is, the reading is presented di- rectly in decibels, and is conveniently scaled 1 v per decade, that is, 50 mv/db; other slopes are easily arranged. in controller modes, the voltage applied to vset determines the power level required at the input to null the deviation from the set point. the output buffer can provide high load currents. the AD8362 is powered down by a logic high applied to the pwdn pin, i.e., the consumption is reduced to about 1.3 mw. it powers up within about 20 s to its nominal operating current of 20 ma at 25?. the AD8362 is supplied in a 16-lead tssop package for opera- tion over the industrial temperature range of ?0 c to +85 c. an evaluation board is available.
rev. 0 e2e AD8362especifications (v s = 5 v, t = 25 c, z o = 50 , differential input drive via balun 1 , vtgt connected to v ref v out tied to v set , unless otherwise noted.) parameter conditions min typ max unit overall function maximum input frequency 2.7 ghz input power range (diff?l) db referred to 50 impedance level, f 2.7 ghz, nominal low end of range into 1:4 balun 1 e52 dbm nominal high end of range +8 dbm input voltage range (diff?l) rms voltage at input terminals, f 2.7 ghz, into nominal low end of range input of the device. 1.12 mv rms nominal high end of range 1.12 v rms input power range (s-sided) single-ended drive, cw input, f 2.7 ghz, into nominal low end of range input resistive network 2 e40 dbm nominal high end of range 0 dbm input voltage range (s-sided) rms voltage at input terminals, f 2.7 ghz nominal low end of range 2.23 mv rms nominal high end of range 223 v rms output voltage range r l 200 to ground nominal low end of range +100 mv nominal high end of range in general, v s e0.1 v +4.9 v output scaling (log slope) 50 mv/db law conformance error over central 60 db range, f 2.7 ghz 0.5 db rf input interface pins inhi, inlo, ac-coupled input resistance single-ended drive, wrt decl 100 differential drive 200 output interface pin vout available output range r l 200 to ground 0.5 4.9 v absolute voltage range v nominal low end of range measurement mode, f = 900 mhz p in = e52 dbm 0.32 0.48 v nominal high end of range measurement mode, f = 900 mhz p in = +8 dbm 3.44 3.52 v source/sink current vout held at v s /2, to 1% change 48 ma slew rate rising c l = open 60 v/ s slew rate falling c l = open 5 v/ s rise time, 10%e90% 0.2 v to 1.8 v, clpf = 0 45 ns fall time, 90%e10% 1.8 v to 0.2 v, clpf = 0 0.4 s wide-band noise clpf = 1000 pf, f spot 100 khz 70 nv/ hz hz hz 2 22 2 2 2 2 2 2 2 2
rev. 0 AD8362 e3e parameter conditions min typ max unit power down interface pin pwdn logic level to enable logic low enables 1 v logic level to disable logic high disables 3 v input current logic high 230 a logic low 5 a enable time from pwdn low to vout within 10% of final value, clpf = 1000 pf 14.5 ns disable time from pwdn high to vout within 10% of final value, clpf = 1000 pf 2.5 us power supply interface pin vpos supply voltage 4.5 5 5.5 v quiescent current 20 22 ma supply current when disabled 0.2 ma 900 mhz dynamic range error referred to best fit line (linear regression) 1 db linearity, cw input 65 db 0.5 db linearity, cw input 62 db deviation vs. temperature deviation from output at 25 c e40 c < t a < +85 c; p in = e45 dbm e1.7 db e40 c < t a < +85 c; p in = e20 dbm e1.4 db e40 c < t a < +85 c; p in = 5 dbm e1 db logarithmic slope 46 50 54 mv/db logarithmic intercept e64 e60 e56 dbm deviation from cw response 5.5 db peak-to-rms ratio (is95 reverse link) 0.2 db 12 db peak-to-rms ratio (wcdma 4 channels) 0.2 db 18 db peak-to-rms ratio (wcdma 15 channels) 0.5 db 1.9 ghz dynamic range error referred to best fit line (linear regression) 1 db linearity, cw input 65 db 0.5 db linearity, cw input 62 db deviation vs. temperature deviation from output at 25 c e40 c < t a < +85 c; p in = e45 dbm e0.6 db e40 c < t a < +85 c; p in = e20 dbm e0.5 db e40 c < t a < +85 c; p in = 5 dbm e0.3 db logarithmic slope 51 mv/db logarithmic intercept e59 dbm deviation from cw response 5.5 db peak-to-rms ratio (is95 reverse link) 0.2 db 12 db peak-to-rms ratio (wcdma 4 channels) 0.2 db 18 db peak-to-rms ratio (wcdma 15 channels) 0.5 db 2.2 ghz dynamic range error referred to best fit line (linear regression) 1 db linearity, cw input 65 db 0.5 db linearity, cw input 65 db deviation vs. temperature deviation from output at 25 c e40 c < t a < +85 c; p in = e45 dbm e1.8 db e40 c < t a < +85 c; p in = e20 dbm e1.6 db e40 c < t a < +85 c; p in = 5 dbm e1.3 db logarithmic slope 50.5 mv/db logarithmic intercept e61 dbm deviation from cw response 5.5 db peak-to-rms ratio (is95 reverse link) 0.2 db 12 db peak-to-rms ratio (wcdma 4 channels) 0.2 db 18 db peak-to-rms ratio (wcdma 15 channels) 0.5 db
rev. 0 e4e AD8362 parameter conditions min typ max unit 2.7 ghz dynamic range error referred to best fit line (linear regression) 1 db linearity, cw input 63 db 0.5 db linearity, cw input 62 db deviation vs. temperature deviation from output at 25 c e40 c < t a < +85 c; p in = e40 dbm e5.3 db e40 c < t a < +85 c; p in = e15 dbm e5.5 db e40 c < t a < +85 c; p in = 15 dbm e4.8 db logarithmic slope 50.5 mv/db logarithmic intercept e58 dbm deviation from cw response 5.5 db peak-to-rms ratio (is95 reverse link) 0.2 db 12 db peak-to-rms ratio (wcdma 4 channels) 0.2 db 18 db peak-to-rms ratio (wcdma 15 channels) 0.4 db notes 1 1:4 balun transformer, m/a-com etc 1.6-4-2-3 2 resistive network consists of 33 shunt and 25 series. 3 see tpc 29 specifications subject to change without notice.
rev. 0 AD8362 e5e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8362 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * supply voltage v pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v input power (into input of device) . . . . . . . . . . . . . . . . 13 dbm equivalent voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 v rms internal power dissipation . . . . . . . . . . . . . . . . . . . . 500 mw
rev. 0 e6e AD8362 pin function descriptions equivalent pin no. mnemonic description circuit 1, 8 comm common connection. connect via low impedance to system common. 2 chpf input hpf. connect to common via a capacitor to determine 3 db point of input signal high-pass filter. 3, 6 decl decoupling terminals for inhi and inlo. connect to common via a large capacitance to complete input circuit. 4 inhi high signal input terminal. part of a differential input port with inlo. circuit a 5 inlo low signal input terminal. part of a differential input port with inhi. circuit a 7p wdn disable/enable control input. apply logic high voltage to shut down the AD8362. 9 clpf connection for loop filter integration (averaging) capacitor, the other pin of which is usually grounded via a resistor to improve loop stability and response time. 10, 16 acom analog common connection for output amplifier 11 vset the voltage applied to this pin sets the decibel value of the required rf input voltage that results in zero current out of pin clpf and thus the loop integrating capacitor. circuit b 12 vout output of error amplifier. in measurement mode, normally connected directly to vset. circuit c 13 vpos connect to 5 v power supply 14 vtgt the logarithmic intercept voltage is proportional to the voltage applied to this pin. the use of a lower target voltage increases the crest factor capacity. circuit d 15 vref general-purpose reference voltage output of 1.25 v (usually connected only to vtgt) circuit e equivalent circuits vtgt acom comm vpos 50k 50k vtgt interface gain = 0.12 circuit d vout acom comm vpos rail-to-rail o/p 2k 500 clpf 0.7v circuit c inhi inlo decl decl vpos comm comm 100 vga vpos 100 circuit a vset acom comm vpos vset interface ~35k ~35k circuit b vout acom comm vpos souce only ref buf 13k 5k ~ 0.35v circuit e
rev. 0 t ypical performance characteristicseAD8362 e7e input amplitude ? dbm 0 ?60 v out ? v 1 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 1.5 2 2.5 3 3.5 4 4.5 0.5 15 900mhz 100mhz 1900mhz ?10 2200mhz 2700mhz tpc 1. output voltage (v out ) vs. input amplitude (dbm), frequencies 100 mhz, 900 mhz, 1900 mhz, 2200 mhz, 2700 mhz, sine wave, differential drive input amplitude ? dbm ?3 ?60 error in v out ? db ?1.5 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 15 900mhz 1900mhz 2700mhz 2200mhz ?2.5 3 100mhz ?10 0 tpc 2. logarithmic law conformance vs. input amplitude, frequencies 100 mhz, 900 mhz, 1900 mhz, 2200 mhz, 2700 mhz, sine wave, differential drive input amplitude ? dbm 0 ?55 v out ? v 0.8 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 1.2 1.6 2.0 2.4 2.8 3.2 3.6 0.4 15 +25 c 4.0 ?40 c +25 c +85 c error in v out ? db +85 c ?40 c ?3 ?2.4 ?1.8 ?1.2 0 0.6 1.2 1.8 2.4 3 ?10 ?0.6 tpc 3. v out and law conformance vs. input am- plitude, frequency 900 mhz, sine wave, temperature e40 c, +25 c, and +85 c input amplitude ? dbm v out ? v +25 c ?40 c +25 c error in v out ? db +85 c ?40 c +85 c ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 15 ?10 0.4 0 0.8 1.2 1.6 2 2.4 2.8 3.6 3.2 4 ?3 ?1.2 ?0.6 0 1.2 1.8 2.4 3 ?1.8 ?2.4 0.6 tpc 4. v out and law conformance vs. input amplitude, frequency 1900 mhz, sine wave, temperature e40 c, +25 c, and +85 c input amplitude ? dbm 0.4 0 ?60 v out ? v 0.8 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 1.2 1.6 2 2.4 2.8 3.6 15 +25 c ?40 c +25 c error in v out ? db +85 c ?40 c 3.2 4 +85 c ?55 ?10 ?3 ?1.2 ?0.6 0 1.2 1.8 2.4 3 ?1.8 ?2.4 0.6 tpc 5. v out and law conformance vs. input amplitude, frequency 2200 mhz, sine wave, temperature e40 c, +25 c, and +85 c input amplitude ? dbm 0 ?60 v out ? v 1 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 1.5 2 2.5 3 3.5 4 0.5 15 wcdma 15 channel cw is95 reverse link wcdma 8 channel ?10 tpc 6. v out vs. input amplitude with different waveforms, cw, is95-reverselink, wcdma 8-channel, wcdma 15-channel, frequency 900 mhz
rev. 0 e8e AD8362 input amplitude ? dbm ?3 ?60 error in v out ? db ?1.5 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 15 ?2.5 3 wcdma 15 channel cw is95 reverse link wcdma 8 channel ?10 0 tpc 7. output error from cw linear reference vs. input amplitude with different waveforms, cw, is95 reverse link, wcdma 8-channel, wcdma 15-channel, frequency 900 mhz input amplitude ? dbm ?3 error in v out ? db ?1.5 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 ?2.5 3 wcdma 15 channel cw wcdma 8 channel wcdma 4 channel ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?10 0 tpc 8. output error from cw linear reference vs. input amplitude with different wcdma channel loading, 4-channel, 8-channel, 15-channel, frequency 2200 mhz input amplitude ? dbm ?3 ?60 error in v out ? db ?1.5 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 15 ?2.5 3 wcdma 8 channel ?10 0 wcdma 15 channel tpc 9. output error from cw linear reference vs. input amplitude, 3 sigma to either side of mean, with wcdma 8-channel, wcdma 15-channel, frequency 1900 mhz input amplitude ? dbm ?3 ?60 error in v out ? db ?1.5 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 15 ?2.5 3 ?10 0 wcdma 8 channel wcdma 15 channel tpc 10. output error from cw linear reference vs. input amplitude, 3 sigma to either side of mean, with wcdma 8-channel, wcdma 15-channel, frequency 1900 mhz input amplitude ? dbm ?3 ?60 error in v out ? db ?1.5 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 15 ?2.5 3 ?10 0 wcdma 8 channel wcdma 15 channel tpc 11. output error from cw linear reference vs. input amplitude, 3 sigma to either side of mean, with wcdma 8-channel, wcdma 15-channel, frequency 2200 mhz input amplitude ? dbm 0 v out ? v 1 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 1.5 2 2.5 3 3.5 4 0.5 ?10 tpc 12. v out vs. input amplitude, 3 sigma to either side of mean, sine wave, frequency 900 mhz, part-to-part variation
rev. 0 AD8362 e9e input amplitude ? dbm 0 v out ? v 1 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 1.5 2 2.5 3 3.5 4 0.5 ?10 tpc 13. v out vs. input amplitude, 3 sigma to either side of mean, sine wave, frequency 1900 mhz, part-to-part variation input amplitude ? dbm ?3 ?55 error in v out ? db ?1.5 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 ?2.5 3 ?10 0 ?40 c +25 c +85 c tpc 14. logarithmic law conformance vs. input amplitude, 3 sigma to either side of mean, sine wave, frequency 900 mhz, temperature e40 c, +25 c, and +85 c input amplitude ? dbm ?3 ?55 error in v out ? db ?1.5 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 ?2.5 3 ?10 0 ?45 c +85 c +25 c tpc 15. logarithmic law conformance vs. input amplitude, 3 sigma to either side of mean, sine wave, frequency 1900 mhz, temperature e40 c, +25 c, and +85 c input amplitude ? dbm ?3 ?55 error in v out ? db ?1.5 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 ?2.5 3 ?10 0 ?40 c +85 c +25 c tpc 16. logarithmic law conformance vs. input amplitude, 3 sigma to either side of mean, sine wave, frequency 2200 mhz, temperature e40 c, +25 c, and +85 c frequency ? mhz 49 900 slope ? mv 49.5 1000 1100 1200 1300 1400 1500 1600 1700 1800 2000 2100 2200 50 51 51.5 2300 52 1900 50.5 2400 2500 2600 2700 +85 c +25 c ?40 c tpc 17. logarithmic slope vs. frequency, temperature e40 c, +25 c, and +85 c frequency ? mhz ?63 900 intercept ? dbm ?58 1000 1100 1200 1300 1400 1500 1600 1700 1800 2000 2100 2200 ?57 ?55 ?54 2300 ?53 1900 ?56 2400 2500 2600 2700 +85 c +25 c ?40 c ?62 ?60 ?59 ?61 tpc 18. logarithmic intercept vs. frequency, temperature e40 c, +25 c, and +85 c
rev. 0 e10e AD8362 temperature ? c ?3 ?40 change in slope ? mv ?1.5 ?30 ?20 ?10 0 10 20 30 40 50 70 80 90 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 ?2.5 3 60 0 1900mhz 900mhz 2200mhz tpc 19. change in logarithmic slope vs. temperature, 3 sigma to either side of mean, frequencies 900 mhz, 1900 mhz, 2200 mhz temperature ? c ?2 ?40 change in intercept ? db ?1.5 ?30 ?20 ?10 0 10 20 30 40 50 70 80 90 ?1 ?0.5 0.5 1 1.5 2 60 0 900mhz 1900mhz 2200mhz tpc 20. change in logarithmic intercept vs. temperature, 3 sigma to either side of mean, frequencies 900 mhz, 1900 mhz, and 2200 mhz slope ? mv/db 0 hits 40 60 80 100 20 48 53 49 50 51 52 tpc 21. slope distribution, frequency 900 mhz intercept ? dbm 0 hits 40 60 70 80 20 50 30 10 ?61 ?58 ?60.5 ?60 ?59.5 ?59 ?58.5 tpc 22. logarithmic intercept distribution, frequency 900 mhz time ? s 0 0 3 2610 14 20 4 4.5 5 2 3.5 2.5 1.5 1 0.5 ?14 rf burst enable ? v ?2 2 4 6 ?6 0 ?4 ?8 ?10 ?12 812 18 16 v out ? v 4 ?30dbm +2dbm ?10dbm ?20dbm 2v/div 0.5v/div rf burst enable v o ut tpc 23. output response to rf burst input for various rf input levels, carrier frequency 900 mhz, c lpf = 0 time ? ms 0 0 3 2610 14 20 4 4.5 5 2 3.5 2.5 1.5 1 0.5 ?14 rf burst enable ? v ?2 2 4 6 ?6 0 ?4 ?8 ?10 ?12 812 18 16 v out ? v 4 0.5v/div 2v/div ?30dbm +2dbm ?10dbm ?20dbm rf burst enable v o ut tpc 24. output response to rf burst input for various rf input levels, carrier frequency 900 mhz, clpf = 0.1 f
rev. 0 AD8362 e11e time ? s 0 0 3 2610 14 20 4 4.5 5 2 3.5 2.5 1.5 1 0.5 ?14 power-down pin ? v ?2 2 4 6 ?6 0 ?4 ?8 ?10 ?12 812 18 16 v out ? v 4 ?30dbm +2dbm ?10dbm ?20dbm 2v/div 0.5v/div power down pin v out tpc 25. output response using power-down mode for various rf input levels, carrier frequency 900 mhz, c lpf = 0 time ? ms 0 0 3 2610 14 20 4 4.5 5 2 3.5 2.5 1.5 1 0.5 ?14 power-down pin ? v ?2 2 4 6 ?6 0 ?4 ?8 ?10 ?12 812 18 16 v out ? v 4 2v/div ?30dbm +2dbm ?10dbm ?20dbm 0.5v/div tpc 26. output response using power-down mode for various rf input levels, carrier frequency 900 mhz, c lpf = 0.1 f time ? ms 0 0 3.5 2610 14 20 4.5 5 5.5 2.5 4 3 2 1.5 1 ?14 power-down pin ? v ?2 2 4 6 ?6 0 ?4 ?8 ?10 ?12 812 18 16 v out ? v 4 v pos 2v/div 1v/div +2dbm ?10dbm ?20dbm ?30dbm tpc 27. output response to gating on power supply for various rf input levels, carrier frequency 900 mhz, c lpf = 0 180 150 120 90 60 30 0 330 300 270 240 210 tpc 28. input impedance, z o = 50 , differential drive temperature ? c ?30 ?40 change in v ref ? mv ?15 ?30 ?20 ?10 0 10 20 30 40 50 70 80 90 ?10 ?5 ?20 ?25 60 0 5 tpc 29. change in v ref vs. temperature, 3 sigma to either side of mean v ref ? v 0 hits 200 300 100 250 150 50 1.230 1.270 1.235 1.240 1.245 1.250 1.260 1.255 1.265 tpc 30. v ref distribution
rev. 0 e12e AD8362 characterization setup equipment the general hardware configuration used for most of the AD8362 characterization is shown in figure 1. the signal source used was a rohde & schwarz smiq03b. a 1:4 balun transformer was used to transform the single-ended rf signal to differential form. for the response measurements in tpc 23 and tpc 24, the configuration shown in figure 2, was used for tpc 25 and tpc 26 the configuration shown in figure 3 was used, and for tpc 27 the configuration shown in figure 4 was used. AD8362 characterization board rfin 3db v out smiq03b rf source pc controller multimeter hp34401a figure 1. primary characterization setup analysis the slope and intercept are derived using the coefficients of a linear regression performed on data collected in its central operat- ing range. error is stated in two forms: error from linear response to cw waveform, and output delta from 25 c performance. the error from linear response to cw waveform is the de cibel difference in output from the ideal output defined by the con- version gain and output reference. this is a measure of the linear ity of the device response to both cw and modulated w ave- forms. the error in db is calculated by subtracting the ideal voltage, i.e., slope times the input level plus the intercept, from the actual input level and dividing this quantity by the slope. error from linear response to cw waveform is not a measure of absolute accuracy, since it is calculated using the slope and intercept of each device. however, it verifies the linearity and effect of modulation on the device response. error from 25 c performance uses the performance of a given device and wave- form type as the reference; it is predominantly a measure of output variation with temperature. tek p5050 vo ltag e probe c1 c2 c3 c4 hpe3631a power supply tek tds5104 scope smt03 signal generator balun 3db comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 rf 50 figure 2. response measurement setup for modulated pulse tek p5050 vo ltag e probe c1 c2 c3 c4 hpe3631a power supply tek tds5104 scope smt03 signal generator balun 3db comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 hp8112a pulse generator rf 50 figure 3. response measurement setup for power-down step tek p5050 vo ltag e probe c1 c2 c3 c4 tek tds5104 scope smt03 signal generator balun 3db comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 rf 50 hp8112a pulse generator 732 0.01 f 100pf 50 ad811 figure 4. response measurement setup for gated supply
rev. 0 AD8362 e13e circuit description the AD8362 is a fully calibrated, high accuracy, rms-to-dc converter providing a measurement range of over 60 db and capable of operation from signals as low in frequency as a few hertz to at least 2.7 ghz. unlike earlier rms-to-dc converters, the response bandwidth is completely independent of the signal magnitude. the e3 db point occurs at about 3.5 ghz. the capacity of this part to accurately measure waveforms having a high peak-to-rms ratio (crest factor) is independent of either the signal frequency or its absolute magnitude, over a wide range of conditions. this unique combination allows the AD8362 be to used with equal ease as a calibrated rf wattmeter covering a power ratio of >1,000,000:1, as a power controller in closed-loop systems, or as a general-purpose rms-responding voltmeter, and in many other low frequency applications. vga b and-gap reference inhi inlo chpf set-point interface offset nulling vset v set vref v ref 1.25v 0.06 v tgt a com vtgt x 2 x 2 v sig v at g output filter c f clpf c lpf external internal resistors set buffer gain to 5 v out v out a com i squ i tgt ?25db to +43db match wide- b and squarers amplitude target for v sig g set figure 5. basic structure of the AD8362 it is essentially the core elements of a high performance agc loop (figure 5), laser-trimmed during manufacture to close tolerances while fully operational at a test frequency of 100 mhz. its linear, wideband, variable gain amplifier (vga) provides a general voltage gain, g set ; this may be controlled in a precisely exponential (linear-in-db) manner over the full 68 db range from e25 db to +43 db by a voltage v set . however, to provide adequate guard-banding, only the central 60 db of this range, from e21 db to +39 db is normally used. later, it will be shown how this basic range may be shifted either up or down, and even extended to >80 db. the vga gain has the form gg vv set o set gns = () exp ? / (1) where g o is a basic fixed gain and v gns is a scaling voltage that defines the gain slope (the db-change-per-volt). note that the gain decreases with v set . the vga output is vgvgv vv sig set in o in set gns == () exp (2) where v in is the ac voltage applied to the input terminals of the AD8362. as will later be explained more fully, the input drive may be either single-sided or differential, but optimum performance at high frequencies will be realized only when using a differential input drive. the effect of hf imbalances when using a single- sided drive is less apparent at low frequencies (say, from 50 hz to 500 mhz), but the peak input voltage capacity is always halved relative to differential operation (see using the AD8362). square-law detection the output of the variable-gain amplifier, v sig , is applied to a wideband square law detector that provides a true-rms response to this alternating signal that is essentially independent of wave- form up to crest-factors of 6. its output is a fluctuating current, i squ , having a positive mean value. this current is integrated by an on-chip capacitance, c f ; this will usually be augmented by an external capacitance, clpf, to extend the averaging time. the resulting voltage is buffered by a gain-of-5 dc-coupled amplifier, whose rail-to-rail output, v out , may be used either for measurement or control purposes. in most applications, the agc loop is closed via the set-point interface pin, vset, to which the vga gain-control voltage v set is applied. in measurement modes, the closure is direct and local, by a simple connection from the output pin vout to vset. in controller modes, the feedback path is around some larger system, but the operation is basically the same. the fluctuating current i squ is balanced against a fixed set-point target current, i tgt , using current mode subtraction. with the exact integration provided by the capacitor(s), the agc loop equilibrates when mean i i squ tgt () = (3) the current i tgt is provided by a second reference squaring cell, whose input is the amplitude-target voltage v atg . this is a fraction of the voltage v tgt applied to a special interface that accepts this input at pin vtgt. since the two squaring cells are electrically identical, and are carefully implemented in the ic, process and temperature-dependent variations in the detailed behavior of the two square-law functions cancel. accordingly, v tgt (and its fractional part v atg ) determines the output that must be provided by the vga in order for the agc loop to settle. since the scaling parameters of the two squarers are accurately matched, it follows that equation 3 will only be satisfied when mean v v sig atg 22 () = (4) in a formal solution, one would then extract the square-root of both sides to provide an explicit value for the root-mean-square (rms) value. however, it is apparent that by forcing this identity, through varying the vga gain, and extracting the mean value by the filter provided by the capacitor(s) the system inherently establishes the relationship rms v v sig atg () = (5) substituting the value of v sig from equation 2, we have rms g v v v v oin set gns atg exp ? () [] = (6) as a measurement device, v in is the unknown quantity and all other parameters can be fixed by design. solving (6): rms g v v v v oin atg set gns [] = () exp (7) so vv rms v v set gns in z = () [] log (8)
rev. 0 e14e AD8362 the quantity v z = v atg / g o is defined as the intercept voltage, since v set must be zero when rms ( v in ) = v z . when connected as a measurement device, the output of the buffer is tied directly to vset, which closes the agc loop. making the substitution v out = v set , and changing the log base to ten, as needed in a decibel conversion, we have vv rms v v out slp in z = () [] log / 10 (9) where v slp is the slope voltage, that is, the change in output voltage for each decade of change in the input amplitude. (note in passing that v slp = v gns log (10) = 2.303 v gns ). in the AD8362, v slp is laser-trimmed to 1 v using a 100 mhz test signal. since a decade corresponds to 20 db, this slope may also be stated as 50 mv/db. it is later shown how the effective value of v slp may be altered by the user. likewise, the intercept v z is also laser-trimmed to 316 v (e70 dbv). in an ideal system v out would cross zero for an rms input of that value. in a single-supply realization of the function, v out cannot run fully down to ground; here, v z is the extrapo- lated value. in measurement modes the output ranges from 0.5 v for v in = 1 mv (inputs are stated as rms values, outputs as dc values), up to a voltage 60 db v in = 1 v, that is, to 3.5 v. figure 6 shows the ideal form of equation 9 scaled as in the AD8362. rms input voltage ? 100 v to 3.2v 0 100 v output voltage 1mv 10mv 100mv 1v 1v 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 figure 6. ideal response of the AD8362 effect of input coupling on the intercept value reductions of v in due to coupling losses directly affect v z . in high frequency applications several factors contribute to the coupling of the source into the ic, including the board and package resonances and attenuation. any uncertainties in the input impedance will result in the intercept expressed in power terms, which is nominally e57 dbm for a 50 system, being less accurately determined than when stated in dbv (that is, in pure voltage) terms. on the other hand, the slope v slp is unaf- fected by all such impedance or coupling uncertainties. offset elimination to address the small dc offsets that arise in the variable-gain amplifier, an offset-nulling loop is used. the high-pass corner frequency of this loop is internally preset to 1 mhz, sufficiently low for most hf applications. when using the AD8362 in lf applications, it can be reduced as needed by the addition of a capacitor from pin chpf to ground having a nominal value of 200 f/hz. for example, to lower the high-pass corner frequency to 150 hz, a capacitance of 0.33 f is required. the offset voltage varies depending on the actual gain at which the vga is operating, and thus, on the input signal amplitude. baseline variations of this sort are a common aspect of all vgas, although more evident in the AD8362 because of the method of its implementation, which causes the offsets to ripple along the gain axis with a period of 6.33 db. when an excessively large value of c hpf is used, the offset correction process may lag the more rapid changes in the vga?s gain, which may increase the time required for the loop to fully settle for a given steady input amplitude. voltage versus power calibration the AD8362 can be used as an accurate rms voltmeter from arbitrarily low frequencies to microwave frequencies. for low frequency operation, the input is usually specified either in volts rms, or in dbv (decibels relative to 1 v rms). driven differentially, the specified input range in dbv runs from e60 dbv to 0 dbv (1 mv to 1 v rms). in these terms, the intercept is at e70 dbv. at high frequencies, signal levels are commonly specified in power terms. in these circumstances, the source and termina- tion impedances are an essential part of the overall scaling. to set the AD8362?s input impedance to 50 , it is necessary to add a resistor of 66.7 across the internal 200 differential input impedance of the ic. (this is discussed further in later sections). for this condition, the intercept occurs at a nominal power level of e57 dbm, and v out can be stated in this way: vp mv db out in =+ () 57 50 (10) where p in is expressed in dbm. for example, an input of e30 dbm will generate an output of 1.35 v. effect of signal waveform the measurement accuracy of an rms-responding device is ideally unaffected by the waveform of the input signal. this is a valuable asset in wideband cdma systems, and in many other modulation modes, where there is a significant amount of random variation of the rf carrier amplitude at baseband frequencies. the high accuracy of the AD8362 in such cases is indicated by the performance curves and in the specifications pages. note that at low frequencies, it is customary to provide a specification of measurement errors due to waveform effects as a function of the crest factor, , rather than in terms of a system-specific modulation mode. when measuring signals whose waveforms have high but brief peak values (that is, having high crest factors), these peaks may be clipped, causing a reduction in the apparent value of the input being measured. this issue is discussed further in connec- tion with the detailed description of the input system. operation at low frequencies in conventional rms-to-dc converters, based on junction tech- niques, the effective signal bandwidth is proportional to the signal amplitude. for a ?1 mhz? rms-to-dc converter, this is the full-scale bandwidth. however, at an input 60 db below full-scale, the bandwidth could be as low as 1 khz. in sharp contrast, the 3.5 ghz bandwidth of the vga in the AD8362 is independent of its gain; and since this amplifier is internally dc-coupled, the system can also be used as a high accuracy rms voltmeter at low frequencies, retaining its temperature-stable decibel-scaled output, for example, in seismic, audio, and sonar instrumentation.
rev. 0 AD8362 e15e in such cases, the input coupling capacitors should be large enough that the lowest frequency components of the signal which are to be included in the measurement are minimally attenuated. for example, for a 3 db reduction at 1.5 khz, capaci- tances of 1 f are needed, since the input resistance is 100 at each input pin, (200 differentially), and we calculate 1/(2 f lp = 1/(c lpf c lpf = 1 nf. time ? s 0 0.4 0.8 1.2 1.6 1.8 2.0 2.6 3.0 0.2 0.6 1.0 1.4 2.2 2.4 2.8 0 16 8243 24048566472 8088 96 output voltage figure 7. typical large-signal response the most satisfactory way to quantify slew-rate limitations is by considering the peak currents that can be generated by the squaring cells. during a fast increase in input level, the peak current into the integrating (loop filter) capacitance, c lpf , is approximately 2.5 ma. the actual value depends on several factors, including the size of the step, and extremes in chip temperature. the voltage across the 1 nf capacitor will thus increase at a rate of nominally 2.5 v/ s. since the output buffer has a gain of 5, the output slew rate will be 12.5 v/ s. the peak rate persists up to a point about 10 db below the final value, after which the response gradually converges on the linear- system response, as noted above. on the other hand, during a fast decrease in input level, the peak current in c lpf in the opposite (discharging) direction is much smaller: it is roughly 25 a. thus, the slew rate for v out in the descending direction is only about 0.125 v/ s for c lpf = 1 nf. to discharge over the full 3 v range (a 60 db reduction of input) requires a time interval of ~24 s. these figures are verified in the results shown in figure 7. alteration of the internal target voltage the AD8362 incorporates several features which extend its versatility. one of these is the ability to alter the target volt- age. as noted, the output of the vga is forced to a value set by the internal bias voltage ( v stp = 0.06 v tgt ) applied to the reference squaring cell. it is normally set to 75 mv dc, by con- necting vtgt to the 1.25 v reference voltage at pin vref. however, it may optionally be varied from 0 v up to 0.24 v ( 4 v at vtgt). note that the sign of this input is unimpor- tant, since it is internally squared. by lowering v spt , the output of the vga needed to balance the output currents of the two matched squaring cells will be simi- larly lowered. this reduces the intercept in precisely the same ratio. thus, if we halve the set-point target voltage by halving the voltage applied to pin vtgt, the intercept moves to the left (to a smaller input level) by 6.02 db. this effectively doubles the measurement system?s sensitivity. furthermore, because the signal amplitude needed to drive the squaring cell is halved, the output stage of the vga now has twice the dynamic headroom (before clipping), and can handle waveforms having crest-factors that are twice as large. figure 8 shows the overall response for an illustrative set of values of vtgt = 0.3 v, 0.533 v, 0.949 v, 1.687 v, and 3.0 v. while this will usually be a fixed dc voltage, it can also be a time- varying, unipolar or bipolar voltage, in which case the overall operation is rather more complex. for example, when v tgt is derived from v out the dynamic range can be extended to over 80 db. examples of such uses of this feature are presented later.
rev. 0 e16e AD8362 rms input voltage relative intercept ? db 100 v1mv 10mv 10v output voltage ? v ?10 ?5 0 5 10 0.2 0.7 1.2 1.7 2.2 2.7 3.2 3.7 0.1v 1v v tgt = 300mv v tgt = 533mv v tgt = 949mv v tgt = 1.69v v tgt = 3.0v figure 8. response with v tgt varied from 0.3 v to 3 v in 5 db steps, showing the proportional shift in intercept effects at each end of dynamic range all agc loops have a limited minimum and maximum input beyond which the system cannot respond correctly. however, the output of a well-behaved system will be in error in such a way as to avoid anomalous measurements. for an input below its minimum capability, the output should not turn around, to falsely indicate a higher input value; for inputs above its maximum capability, the output should not fold over, and return to some lower value. the actual behavior of the AD8362 under these conditions can be seen in the set of plots in figure 8, the lower panel of which shows the deviation from the ideal response with a slope of 50 mv/db. for inputs below a certain level, corresponding to the point at which the vga is operating at its maximum gain, its output can no longer meet the rms amplitude target set by v tgt , so the output moves quickly to its minimum value, in an attempt to provide the needed extra gain. as v tgt is altered, the corresponding end-limit voltage moves to the left or right. on the other hand, when the input is above a certain upper limit, where the vga gain has been driven to its minimum gain, any further increase will drive its output well above the target voltage needed to balance the loop, and the resulting integration of this internal error signal causes v out to rise abruptly. in either case, this output takes on a safe value, and does not fold back under any conditions. the dynamic range, the db distance between these limits, is not basically dependent on vtgt. the middle line in the plots of figure 8 (vtgt = 0.949 v), extends from 0.5 mv to 1.5 v between the 1% error points; the dynam ic range is thus slightly over 68 db. for other values of v tgt , this basic 68 db range just moves to the left or the right. decl inlo inhi decl vga comm comm v in vpos vpos figure 9. input protection at inhi and inlo pins input protection like all robust ics, the AD8362 requires input protection against high voltage transients at the input (esd), but the techniques normally employed for this purpose, based on breakdown diodes from the input pins inhi and inlo to the supply pins vpos and comm cannot be used here, since this raises the risk of excessive signal coupling to internal nodes at the upper end of the frequency range, due to feedthrough in the capacitances of these diodes. package inductances cause all internal nodes, including the supply and common lines, to have a significant impedance back to the external ground plane; even small distur- bances on these nodes can cause anomalous operation. this risk is particularly evident since the main amplifier in the AD8362?s vga (an advanced x-amp ) operates at full gain under all conditions, while the signal input is variably attenu- ated. since this attenuation may be as high as 70 db, very small feedthrough effects in the 0.5 ghze3 ghz range can have a pronounced impact on measurement accuracy. figure 9 shows the protection method used. the multiple diodes arranged in back-to-back pairs limit the voltage swing on the input pins by clamping to the two decl pins, which form a common ac low impedance node for the attenuators, indepen- dently grounded via two external capacitors. the hf currents in the capacitances of these diodes are thus shunted directly to a signal null-point. an unavoidable consequence of this method is that the diodes will forward-conduct when the input amplitude is sufficient. this is not an all-or-nothing effect, of course; they shunt the input progressively as the signal increases. this conduction will be strongest at high temperatures, when the forward drop voltage of these diodes is lowest. the overall consequence is that high
rev. 0 AD8362 e17e amplitude peaks will be clamped, to a greater or lesser degree. this will affect the measurement accuracy at the top extreme of the dynamic range whenever the signal waveform has a high crest factor. these effects are, of course, included in the overall performance specifications. power-enable response time the operating and stand-by currents for the AD8362 at 27 c are 24 ma and 275 a, respectively; their variations versus temperature are shown in tpc 31. the power-down mode is activated by a logic hi on pin pwdn. when the shut-down feature is used, the normal operating conditions are restored relatively quickly when this pin is taken lo. figure 10 shows typical response times for a midscale signal (v in = 50 mv) . the output rises to within 0.1 db of its steady- state value in about 20 s; the reference voltage is available to full accuracy in a much shorter time. this wake-up response will vary in detail depending on the input coupling means and the capacitances c dec , c hpf , and c lpf . these results are for a measurement system operating in the 0.8 ghz to 2 ghz range, balun-coupled at the input port, with cdec = 1 nf, chpf = 0, and clpf = 1 nf. time ? s 0 2.2v 2.19v 2.18v 1.26v 1.25v 1.24v 10 20 30 40 reference voltage output voltage 1db 0.1ma 0.27ma 1ma 10ma 24ma figure 10. typical wake-up response; t 0 = 10 s using the AD8362 the AD8362 requires a single supply of nominally 5 v; its per- formance is essentially unaffected by variations of up to 10%, the range over which the stated specifications apply. supplies as low as 2.7 v may be used with some loss of performance at high inputs and at temperature extremes. the AD8362 is disabled by a logic hi on the pwdn pin, which may be directly grounded for continuous operation, when the supply current at 27 c is nominally 24 ma and essentially inde- pendent of supply voltage. when powered down by a lo on pwdn, the supply current is reduced to about 275 a. basic connections the supply is connected to pin vpos, using the decoupling network shown in figure 11, whose capacitors must provide a low impedance over the full frequency range of the input, and should be placed as close as possible to the vpos pin. two different capacitors are used in parallel to reduce the overall impedance, since these will have different resonant frequencies. however, the measurement accuracy is not critically dependent on supply decoupling, since the high frequency signal path is confined to the relevant input pins. it is more important that the lead lengths to inhi and inlo, and in the decoupling capacitors from both of the decl pins to ground, and the connections from comm to the ground plane all use the shortest possible connections. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf 1nf v out AD8362 signal input z = 2 100 1mv ? 1v rms logic hi for power-down c dec c lpf v s +5v nom, @24ma 0.1 f 3.3 c cpl c dec c dec figure 11. basic measurement mode connections main modes of operation both measurement and controller modes are supported by the AD8362. typical connections for the measurement mode, which may also be viewed as the rms voltmeter mode, are also illustrated in figure 11. the output, v out , is proportional to the logarithm of the rms magnitude of the input signal (that is, a linear-on-db response). when used in an accurately known system impedance (but only then), the output is a scaled decibel measurement of the power represented by the input voltage. the choice of the capacitances c cpl , c dec , c hpf , and c lpf , will depend on the lowest frequency to be included in the measurement spectrum. the default values shown support operation down to 100 hz. using a large enough value of c lpf (10 f) to ensure sufficient filtering at this low input frequency, the response time is approximately 20 ms over most of the dynamic range. in high frequency applications, this capacitor will be much smaller, and will usually be chosen to minimize the response- time, consistent with well-behaved large-signal behavior. in this figure, c hpf is also shown as 10 f, to lower the high-pass corner to about 90 hz. however, no capacitor will be needed here in most hf applications, since the internally-set high-pass corner is at about 2 mhz. now briefly comparing the controller mode, illustrated in figure 12, the AD8362 is here used to monitor the output of a variable-gain (or variable output power) signal processing element, frequently a power amplifier, and adjust its output to a desired target value (the set-point), under the control of vset. in this mode, its function is somewhat like an rf comparator. with the path from vout to vset broken, any input larger than the corresponding set-point causes v out to rail to its maximum value (which might loosely be viewed as a logic hi). for inputs smaller than the set-point, the controller?s output will fall to a near-ground level (logic lo). using the AD8362 simply as a threshold detector, this viewpoint may be useful, but in most applications it is an oversimplification. the AD8362 will invariably operate with the control loop closed, either locally, with vout connected to vset (as in measurement mode), or globally, via some external nonlinear element (as in control- ler mode).
rev. 0 e18e AD8362 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf 1nf v out rail-to-rail control output AD8362 signal input z = 2 100 1mv ? 1 v rms this connection sets chip-enable 1nf 300pf v s +5v nom, @24ma 0.1 f 3.3 c cpl 1nf nc set-point input 0v?3.5v no connection for f >10mhz figure 12. basic controller mode connections controller mode operation is more closely analogous to that of a classical proportional/integral/derivative (pid) loop. the error corresponding to the decibel deviation from the set-point is integrated, by current into a capacitor (the sum of the internal and external capacitance c lpf ), until such deviation is nulled. this action provides the fundamental proportional part of the loop response (although v out has decibel scaling). the q of this system can be adjusted to minimize the loop response time by including a resistor in series with c lpf , generating a trans- mission zero, which provides the derivative term of a standard pid loop. as a simple example, assume that the AD8362 operates at an input power level of e20 dbm re: 50 . connected in the mea- surement mode it will generate a vout of 2.00 v (since this input is 40 db above the intercept at e60 dbm, and is scaled 50 mv/db. rearranged to the controller mode, with exactly this voltage now externally applied to pin vset, the loop forces vout to the control voltage required by the gain element to provide a power sample of e20 dbm. of course, any control loop of this sort will only operate cor- rectly if vset corresponds to a power level (or a small sample of such) than can actually be provided by the external gain element. when this is a power amplifier, the inclusion of the required amount of rf attenuation ensures this condition. in certain instrumentation situations, it may be necessary to pro- vide some low noise gain ahead of the AD8362?s input. these two primary modes of use of are now discussed in more detail, with emphasis on practical considerations. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf 1nf v out rail-to-rail control output AD8362 signal input z = 50 1nf 300pf v s +5v nom, @24ma 0.1 f 3.3 200 1nf nc 1:4 z-ratio (1:2 turns ratio) figure 13. connections for rf power measurement operation in measurement modes figure 13 shows the general connections for operating the AD8362 as an rf power detector, more correctly viewed as an accurate measurement system. the full performance potential of this part, particularly at very high frequencies (above 500 mhz) will only be realized when the input is presented to the AD8362 in differential (balanced) form. in this illustrative example, a flux-coupled transformer is used at the input. having a 1:4 impedance ratio, (1:2 turns ratio) the 200 differential input resistance of the AD8362 becomes 50 at the input to the transformer, whose outputs can be connected directly to inhi and inlo. if a center-tapped transformer is used, connect the tap to the decl pins, which are biased to the same potential as the inputs (~3.6 v). over the 0.9 ghze2.2 ghz range a transmis- sion line transformer (balun) may be used, as explained later. (the evaluation board is supplied with a m/a-com etc1.6-4-2-3, 0.5 ghze2.5 ghz, 4:1 balun). the output in this mode of use is a continuous, decibel-scaled voltage: vppmvdb out in z = () 50 (11) ranging from about 0.5 v to 3.5 v. the equivalent input power p in is expressed in dbm, (decibels above 1 mw) in a particular system impedance, which in this case is 50 . the intercept, p z , is that input power for which the back-extrapolated output crosses zero. expressed as a voltage it is 0.447 mv rms (e67 dbv, laser-calibrated at 100 mhz), corresponding to a p z of e60 dbm in 200 . however, the 1:2 turns ratio of the transformer halves the required input voltage, which moves the intercept down by 6 db, to 0.224 mv rms (e73 dbv) at the transformer?s input. impedance mismatches and attenuation in the coupling elements will significantly affect the intercept position. this error will be stable over temperature and time, and thus can be removed during calibration in a specific system. the logarithmic slope of 50 mv/db varies only slightly with frequency; corrected values for several common frequencies are provided in the specifications. law conformance error in practice, the response will deviate slightly from the ideal straight line suggested by equation 11. this deviation is called the law conformance error. in defining the performance of high accuracy measurement devices, it is customary to provide plots of this error. in general terms, it is computed by extracting the best straight line to the measured data using linear regres- sion over a substantial region of the dynamic range, and under clearly specified conditions.
rev. 0 AD8362 e19e input amplitude ? dbm 0.2 v out ? v 0.8 1.1 1.4 1.7 2.0 2.3 2.9 3.5 0.5 3.8 error in v out ? db ?3 ?1.5 ?1 ?0.5 0.5 1 1.5 2 2.5 ?2 ?2.5 3 2.6 3.2 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?5 0 5 10 15 ?10 0 ?40 c +25 c +85 c + 25 c +85 c ?40 c figure 14. output voltage and law conformance error, at t a = e40 c, +25 c and +85 c figure 14 shows the output of the circuit of figure 13 over the full input range. the agreement with the ideal function (law conformance) is also shown. this was determined by linear regression on the data points over the central portion of the transfer function (35 mv to 250 mv rms) for the 25 c data. the error at +25 c, e40 c, and +85 c was then calculated by subtracting the ideal output voltage at each input signal level from the actual output, and dividing this quantity by the mean slope of the regression equation to provide a measurement of the error in decibels (scaled on the right-hand axis of figure 14). the error curves generated in this way reveal not only the deviations from the ideal transfer function at a nominal tempera- ture, but also all of the additional errors caused by temperature changes. notice there is a small temperature-dependence in the intercept (the vertical position of the error plots); this variation is within 0.5 db at high powers. figure 14 further reveals that there is a periodic ripple in the conformance curves. this is due to the interpolation technique used to select the signals from the attenuator, not only at discrete tap points, but anywhere in between, thus providing continuous attenuation values. the selected signal is then applied to the 3.5 ghz, 40 db fixed gain amplifier in the remaining stages of the AD8362?s vga. an approximate schematic of the signal input section of the AD8362 is shown in figure 15. the ladder attenuator is composed of a eleven sections (twelve taps), each of which progressively attenuates the input signal by 6.33 db. each tap is connected to a variable-transconductance cell, whose bias current determines the signal weighting given to that tap. the interpolator determines which stages are active, by generating a discrete set of bias currents, each having a gaussian profile. these are arranged to move from left to right, thereby determining the attenuation applied to the input signal, as the gain is progressively lowered over the 69.3 db range under control of the v set input. the detailed manner in which the transconductance of adjacent stages varies, as the virtual tap point sli des along the attenuator, accounts for the ripple observed in the conformance curves. its magnitude is slightly temperature-dependent, and also varies with frequency (see tpcs 3e5). notice that the system?s responses to signal inputs at inhi and inlo are not completely independent: these pins do not constitute a fully floating differential input. to fixed gain stage gm gm gm gm attenuation control guassian interpolator stage 1 6.33db stage 11 6.33db inhi stage 2 6.33db decl inlo figure 15. simplified input circuit alternative input coupling means the input stages of the AD8362 are optimally driven from a fully-balanced source, which should be provided wherever possible. the ac low side of both halves of the attenuator internally connect to the decl pin, which is therefore the rf signal low terminal for both inhi and inlo. in many cases, unbalanced sources can be applied directly to one or the other of these two pins. the chief disadvantage of this driving method is a reduction in dynamic range, particularly at very high frequencies. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 rf input z = 50 nc this input is driven 1nf 1nf r sh decl and inlo are not driven figure 16. input coupling from a single-ended source figure 16 illustrates one of many ways of coupling the signal source to the AD8362. since the input pins are biased to about 3.6 v (for v s = 5 v) dc-blocking capacitors are required when driving from a grounded source. for signal frequencies >5 mhz, a value of 1 nf is adequate. while either inhi or inlo may be used, the former is chosen here, and inlo is connected to the low side of the source. the resistor rsh is not needed if a 100 termination is acceptable. the corresponding intercept will still be e67 dbv, that is, 447 v rms. however, specified in power terms re: 100 , the p z is now at 2 nw, or e57 dbm. for a source termination of 50 , the internal 100 from inhi to decl must be shunted by a chip resistor of 100 . at high frequencies, a low attenuation pad at the input will improve the vswr. for example, with a resistor of r sh = 33 and an added resistor of 25 from the source to inhi, a termination of 50 is provided, with 6 db of attenuation, raising the intercept to e48 dbm. use of a narrow-band input match while transformers offer the simplest method for providing single-sided to balanced conversion, a good alternative is the use of a specially designed narrow-band lc network, shown in
rev. 0 e20e AD8362 figure 17, which also provides an input match. using this basic formulation, the match is to 50 , with a voltage gain of 1.5 (3.56 db) from the input connector to the AD8362. this network is specially designed to provide a high degree of amplitude bal- ance at inhi and inlo, as well as an exact phase inversion. the narrow-band match provides a useful degree of frequency selectivity, and the capacitors also serve to provide the required dc blocking. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 rf input z = 50 l nc these inputs are equal in amplitude and of opposite sign c2 c1 100 figure 17. narrow band reactive input coupling the network can readily be scaled to other frequencies by vary- ing the product lc, while keeping the ratio l/c constant to preserve a 50 input impedance. table i provides some spot values; these take into account the reactive z in of the AD8362. table i. suggested components for narrow-band 50 match frequency l c1 c2 (mhz) (nh) (pf) (pf) 1 21850 2230 2765 2 10925 1115 1383 5 4370 446 553 10 2185 223 276 20 1093 112 138 50 437 45 55 100 220 22 27 200 100 10 12 500 40 3.9 4.7 this coupling method can be used down to much lower frequen- cies than shown in table i, simply by multiplying the 1 mhz component values proportionally. the effects of the reactive com- ponents of the AD8362?s inputs above 500 mhz may require some fine-tuning of the suggested values, and in the gigahertz region the input coupling will usually be more effectively imple- mented using a balun. uncertainties in r in and power calibration in all these cases where a 50 to 200 transformation is implemented, the voltage gain is only nominally f hp of this filter must be below that of the lowest input signal in the desired measurement bandwidth frequency in order to properly measure the amplitude of the input signal. the required value of the external capacitor is given by cfffinhz hpf hp hp = () 200 (12) thus, for operation at frequencies down to 100 khz, c hpf should be 2 nf. in the standard connections for the measurement mode, pin vset is tied to vout. for small changes in input amplitude (a few decibels), the time-domain response of this loop will be essentially linear, with a 3 db low-pass corner frequency of nominally f lp = 1/(c lpf f lp = 3 mhz. for operation at lower signal frequencies, or whenever the aver- aging time needs to be longer, use cfff in hz lpf lp lp = () 09 . (13) when the input signal exhibits large crest factors, such as a w-cdma signal, it will be found that c lpf must be much larger than might at first seem necessary. this is due to the presence of significant low frequency components in the complex, pseudo-random modulation, which will generate fluctuations in the output of the AD8362. use of nonstandard target voltages an external connection between vref and vtgt sets up the internal target voltage, that is, the rms voltage that must be pro- vided by the vga in order to balance the agc feedback loop. in the default scheme, the v ref of 1.25 v positions this target to 0.06
rev. 0 AD8362 e21e in principle, this doubles the peak crest factor that may be handled by the system. if v tgt is reduced too far, the accuracy and stability of the intercept will be compromised. the currents generated by the transconductance mode squaring cells become smaller by the square of the ratio. thus, a factor of 5 reduction in v tgt w ill lower the signal currents in the squaring cells by a factor of 25. as well as making the system more sensitive to small static errors (offsets) in the post-detection circuitry, such a reduction will also reduce the peak slew rate, and a suitable adjustment to the value of c lpf will be needed to maintain a given agc loop bandwidth. on the other hand, increasing the target voltage can improve the accuracy and stability of the intercep t for low crest factor signals. thus, using v tgt = 2.5 v, the peak output cur- rents of the squaring cell are quadrupled, and the peak slew rate is increased by the same factor. clpf should be increased to maintain an adequate stability margin in the agc loop. in many applications, it will be useful to use a nonstandard value of v tgt to shift the measurement range by a constant amount, to accommodate either a reduced or increased range of signal inputs. the dynamic span remains >60 db for such changes. this technique will be particularly useful when the sensitivity can be lowered, by raising vtgt, and there is little expectation of high crest factor signals. adjusting the intercept another way to exploit the effect of v tgt is to use it to intro- duce an adjustment to the log intercept, represented by the voltage v z in equation 14. formally, this can be expressed in terms of a modified value of v z ' : vvv v zz tgt '. = 125 (14) a lower v tgt effectively increases the sensitivity of the mea- su rem en t system, which is just another way of stating that the intercept moves to a lower value. this raises v out for all input amplitudes, as was demonstrated earlier by the plots shown in figure 8. this control of the measurement system?s intercept could therefore be effected by applying the output of a dac to pin vtgt, if that suits the overall objectives of an application. for many purposes, a small manual adjustment range of 3 db will be sufficient. this can be implemented as shown in figure 18. here, the largest fraction of v tgt is still provided by the built-in reference, to minimize the sensitivity to supply voltage variations, but now a variable component is provided by the trim network. for a 5 v supply, this added component of v tgt is zero when vr1 is centered. with the slider closest to ground, v tgt is lowered by 366 mv, which corresponds to a 3 db decrease in intercept; in the opposite condition, it is raised by 518 mv, which increases the intercept by 3 db. that is, v tgt ranges from 1.25 v/ 2 2 that is fed back to the set-point interface, at pin vset. when the full signal from vout is applied to vset, the slope assumes its nominal value of 50 mv/db. it can be increased by including an attenuator between these pins, a shown in figure 19. m oderately low resistance values should be used, to minimize scaling errors due to the 70 k input resistance at the vset pin, but keep in mind that this resistor string also loads the output, and it will eventually reduce the load-driving capabilities if very low values are used. to calculate the resistor values, use rrs d 12 50 1 = () 'e (15) where s d is the desired slope, expressed in mv per db, and r2' is the value of r2 in parallel with 70 k . for example, using r1 = 1.65 k and r2 = 1.69 k (r2' = 1.649 k ), the nominal slope is increased to 100 mv/db. this choice of scaling will be useful when the output is to be applied to a digital voltmeter, since the displayed number reads as a decibel quantity directly, with only a decimal-point shift. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 v out r1 r2 figure 19. external network to raise slope
rev. 0 e22e AD8362 operation at high slopes is useful when a particular sub-range of the input is to be measured in greater detail. however, a mea- surement range of 60 db would correspond to a 6 v change in v out at this slope, exceeding the capacity of the AD8362?s output stage when operating on a 5 v supply. this requires that the intercept is repositioned to place the desired sub-range within a window corresponding to a output range of 0.2 v v out 4.8 v, a 46 db range. using the arrangement shown in figure 20, an output of 0.5 v corresponds to the lower end of the desired sub-range, and 4.5 v corresponds to the upper limit, with 3 db of margin at each end of the range, which is nominally 3 mv rms to 300 mv rms, with the intercept at 1.9 mv rms. note that r2 is connected to vref rather than ground. r3 is needed to ensure that the AD8362?s reference buffer, which can sink only a small current, is cor- rectly loaded. it will be apparent that a variable attenuation factor based on this scheme could provide a manual adjustment of the slope, but there will be few situations in which this will be of value. when the slope is raised by some factor, the loop capacitor c lpf should be raised by the same factor to ensure stability and to preserve a chosen averaging time. the slope can be lowered by placing a two-resistor attenuator after the output pin, following standard practice. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 v out r1 4.02k r2 4.32k r3 2k figure 20. scheme providing 100 mv/db slope for operation over a 3 mv to 300 mv input range envelope elimination mode the vtgt input can be used to track the am modulation envelope on an rf signal, to effect a form of envelope elimina- tion. the modulation waveform must be known, and a sample available as a baseband voltage. using this voltage as v tgt , the AD8362 tracks this envelope when demodulation is effected by the squaring cell. so, if the envelope output of the main ampli- fier should, say, double over some interval, while the target voltage that satisfies the agc loop criterion also doubles, the net effect will be that the gain of the amplifier will not need to change, in order to keep the loop balanced. that being the case, the gain-control voltage v set likewise does not need to change. it follows that the output will be free of fluctuations. in the measurement mode, that voltage is also the output, so it also remains at a constant value as the modulation varies the input magnitude. the bandwidth of the dc-coupled amplifier in the AD8362 that buffers v tgt has been kept high (~300 mhz), so that even fast am modulation envelopes can be accurately tracked. figure 21 shows an illustrative realization. as depicted in the top panel of figure 22, the input to the AD8362 is a pure, ideal, sinusoidal 100 mhz carrier that is amplitude modulated at 100 khz by another pure sine wave. a suitably scaled sample of the modulation voltage is also applied to the vtgt pin. in this illustrative example, its average value is 1.25 v (the normal bias level for v tgt ) and the amplitude is 0.75 v. so v tgt ranges from 0.5 v to 2 v, corresponding to a factor of 4 change (16 db) in the target voltage over each cycle of the modulation. t he resulting v out waveform is of essentially constant value at about 2.5 v, as shown in figure 22; this is compared with the deeply fluctuating output for a fixed v tgt of 1.25 v. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf 1nf v out AD8362 amplitude modulated signal input 1nf c lpf v s +5v nom, @ 24ma 0.1 f 3.3 1nf nc ba seband replica of modulated input signal envelope nc figure 21. envelope elimination using the vtgt interface time ? s rf input ? v 0.2v ?0.2v 1v 0 2v 3v 0v 2v 1v 0v v tgt ? v v out ? v fixed target voltage (1.25v) with fixed target voltage with varying target voltage varying target voltage 10 20 30 40 figure 22. waveforms for envelope elimination scheme operation in controller modes in order to fully understand this section, it is important to first read the preceding discussion of measurement modes, since there are only a few differences in operation and connections. when used in controller applications, the basic objective is to use the AD8362 as a level-sensing element, in such a way that its output, here v apc , moves in a direction that increases the controlled signal when the input sample is too low, and vice versa. a general scheme is illustrated in figure 23.
rev. 0 AD8362 e23e v s se t-point voltage input 0.5v?3.5v c ontrolled system (output power decreases as vapc increases) input ou tput va p c s ystem input s ystem ou tput c lpf 1nf 1nf 1nf r sh = 100 for 50 termination nc 0.1 f 1nf 1nf 3.3 r sh 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 figure 23. generalized control loop using the AD8362 since the AD8362 integrates any input error, relative to the set- point, and ideally would fully null this error over an appropriate time interval, it follows that v apc will swing rail-to-rail over a very narrow range of inputs. in practice, a few millidecibels of amplitude deviation at the input will fully swing the output. the signal input level at which this occurs (the set-point) is determined by the control voltage, v set . this voltage defines the narrow range of the ac input over which the AD8362?s out- put is most sensitive to the absolute input magnitude. in base stations, for example, v set will often be delivered by the ramp dac, and the set-point will be a rapidly varying sequence of levels, during the ramp-up and ramp-down intervals of each burst, as well as with output power demand variations from one channel to another. every value of v set maps uniquely to a specific rms value at its input. thus, the major loop shown in figure 23 forces the sys- tem being controlled, s, to deliver exactly this level (which may be either in voltage form, or as a sample of the power output of s). this mode of operation is therefore just an extension of the measurement mode, having exactly the same scaling (slope and intercept) at the vset pin. when the system in figure 23 is an rf power amplifier (pa), a practical consideration immediately comes to our attention. frequently, the gain (and thus output power) is arranged to increase in response to an increasing positive voltage applied to their gain control pin. however, the AD8362?s output tends toward higher values as its input crosses over the level corre- sponding to the set-point, which would cause the pa?s output to increase further. in other words, the feedback polarity is reversed, forcing the control loop to latch up at one of its power extremes. an increasing number of modular pas feature a control polarity that reduces the power output with increases in control voltage. these can be controlled directly from the vout pin of the AD8362. elsewhere, it is necessary to provide the sign inversion using a low noise buffer. this amplifier may also include provi- sions to ensure that the pa is never driven beyond its safe limits. the complete details of such a control system depends on many factors, and this example shows only generic aspects of the design. use of an input balun a balun (balance to unbalance) is used either to transform differential rf signals to single-ended form or in reverse, to convert single-sided signals to differential form. a typical balun consists simply of a short length of transmission line (miniature coax, or twisted pair) through which the signal passes without significant degradation, wound on a former (often a ferrite) to generate a series-mode inductor having a high reactive impedance, compared to the through-mode impedance of the transmission line, which is often 50 . high frequency common-mode voltages applied to the input of this line are sustained across this series reactance, and do not appear at the loaded side of the line. on the other hand, the through-mode bandwidth is very high, and the losses incurred in a short line of this sort are trivial. baluns of slightly more elaborate construction can provide an impedance transformation, usually designated by their imped- ance ratio, for example, 4:1, which becomes a 1:4 ratio when used in reverse, in order to convert a single-sided signal to the balanced form, as is desirable in driving the AD8362, while also presenting a 50 input interface. the evaluation board for the AD8362 includes such a 1:4 balun, part number m/a-com etc1.6-4-2-3, providing low loss coupling from 0.5 ghz to 2.5 ghz and an impedance transfor- mation from the board?s 50 input (at the sma connector) to the 200 differential input resistance of the AD8362. at high frequencies, the actual impedance at the connector will be influenced by reactive aspects of the ic?s input impedance. since these can alter the magnitude of the input voltage, the logarithmic intercept cannot be precisely specified. however, the shift will be temperature-stable. note that the balun used here increases the signal voltage by the square root of its impedance ratio of 4:1, in this case by a factor of two. the use of a transformer to match the 500 source to the 200 load presented by the AD8362 thus increases the effective sensitivity of the measurement system by 6 db, whether specified in dbv or dbm terms at the input to the transformer. general applications the unusual versatility of the AD8362 opens up many new possibilities whenever an element having an accurate rms response is needed. while developed primarily to address the need for true-power measurement in communications systems operating at frequencies as high as 2.7 ghz, the AD8362 is capable of meeting the requirements of instrumentation at much lower frequencies. as noted earlier, the AD8362 is unique in provid- ing rms-to-dc conversion with a completely constant bandwidth, regardless of signal amplitude, and in providing a calibrated linear-in-db measurement. caution: the applications shown here are provided only for illustrative purposes, and should not be regarded as ready for immediate incorporation into a user?s system. they have been validated for the present purpose by simulation studies.
rev. 0 e24e AD8362 rms voltmeter with >100 db dynamic range the 60 db range of the AD8362 can be extended by adding a stand-alone vga as a preamplifier, whose gain control input is derived directly from vout. this extends the dynamic range by the gain control range of this second amplifier. when this vga also provides a linear-in-db (exponential) gain control function, the overall measurement remains linearly scaled in decibels. the vga gain must decrease with an increase in its gain bias, like the AD8362. it is convenient to select a vga needing only a single 5 v supply, and capable of generating a fully balanced differential output. all of these conditions are met by the ad8330. figure 24 shows the schematic. the signal can be applied to the ad8330 in either single-sided or differen- tial form, using a variety of coupling arrangements (see its data sheet for more information). input (see ad8330 data sheet) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 vmag comm cmgn vdbs mode inlo inhi vps1 cmop oplo ophi vps0 cntr vpos ofst enbl ad8330 6.04k 3.6v 10 f 402k 10 f v out 3.3 5v 3.3 3.3 3.6v all unmarked capacitors are 0.1 f c flt 18nf figure 24. rms voltmeter with >100 db dynamic range the basic gain of the ad8330 varies from 0 db to 50 db. here, it is raised 8 db by driving vmag from the 1.25 v available from the AD8362, whose 200 loading on the 150 r out of the ad8330 in turn lowers the overall gain by 5 db. the peak gain is thus ~53 db. (mismatches between the on-chip resistors in each ic can cause a gain error of up to 1.3 db). using the ad8330?s inverse gain mode (mode pin low) its gain decreases on a slope of 30 mv/db to a minimum value of 3 db for a gain voltage (v dbs ) of 1.5 v. v dbs is 40% of the AD8362?s output. over the 3 v range from 0.5 v to 3.5 v the gain of the ad8330 varies by (0.4 hz 22 hz z 2 hz 2 z 2 2 2 2 2 2 2 22 2
rev. 0 AD8362 e25e connections; for present purposes, r1 is omitted and r2 is short-circuited. for small signal inputs, v out is also small, and the target is well below the normal 75 mv (with 1.25 v applied to vtgt). the lower target means that the AD8362?s vga output does not have to be as large as normal, which increases the input sensitiv- ity. as the signal increases, and thus v out , so does the target voltage, which progressively shifts the required vga input to a higher level. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 v out r2 r1 figure 26. rf power meter with 80 db range for example, a 10:1 change of v tgt from 0.35 v to 3.5 v will shift the intercept by 20 db. this has the effect of stretching the measurement range by the same amount, from >60 db to more than 80 db. so the slope decreases, to about 40 mv /db, because a larger input range is now represented by the same 3.15 v. the simulation results shown in figure 27 compare the expanded range response with that for a fixed v tgt . the upper end of the measurement range is extended from 1.5 v to over 4 v (limited by the input protection). however, it will be apparent that the transfer function is no longer a simple logarithmic law; further consideration shows that the modified function is nonanalytic. nevertheless, this function is dependable, and it remains as stable over supply and temperature variations as in the normal mode. a good approximation is provided by vv vv mv out slp in z in = () () []
' log e . log 10 10 3 11 3 (16) rms input voltage deviation ? db 100 v 1mv 10mv 10v output voltage ? v 0 5 10 15 0 1 3 4 0.1v 1v 2 v tgt = v out v tgt = 1.25v v tgt = v out v tgt = 1.25v figure 27. dynamic range expansion using v tgt = v out where the modified slope voltage v slp ' is 0.868 v, that is, 43.4 mv/db. using this expression, the dynamic range is 86 db to the 0.5 db error points (0.2 mv v in 4 v). the actual range will be reduced in practice by the effects of the AD8362?s input-referred noise at low inputs. if the basic 60 db+ range is only slightly less than required in a particular application, then just some fraction of v out can be summed with a part of v ref to the vtgt pin, which is why r1 and r2 were included. the output now conforms in general terms to the formula vv vvk v out slp in z c in = () () []
' log ' e log 10 10 3 (17) where the correction factor kc introduces the required nonlinear correction to minimize the law-conformance error. table ii provides several representative spot values, using progressively greater amounts of dynamic range extension. table ii. suggested values for use in scheme of figure 23 r1 r2 vslp' vz' k c ( )( ) (v/decade) (mv) (m) o/c s/c 0.868 0.334 11.3 1904 96 0.870 0.336 10.4 1346 654 0.890 0.333 6.5 872 1128 0.914 0.340 3.7 480 1520 0.942 0.355 1.5 200 1800 0.972 0.380 0.5 high slope detectors centered on a narrow window the situation often arises in system monitoring in which an input signal varies by much less than 60 db, and the highest possible sensitivity and accuracy of measurement is required within a narrow window of input magnitudes. adapting the AD8362 to this task requires that the slope be increased, and the intercept repositioned. using an attenuator from vout to vset, any slope >50 mv/db can be realized. then, using a fraction of v ref (or external reference voltage) the particular region of the dynamic range to be measured can be positioned wherever desired. in these high slope applications, the full rail- to-rail output swing of the AD8362 can be exploited. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 v out r2 r1 intercept offset vo ltag e , v shift slope r1 r2 (v/dec) (k )(k ) 2 4.02 4.32 4 8.66 3.01 5 8.66 2.15 10 9.1 1.02 figure 28. slope and intercept adjustment figure 28 shows the basic connections for this mode of use; the intercept repositioning voltage v shift can be introduced by adding a third resistor from vref to vset, with recalculated values of r1 and r2, or by using an external voltage source. figure 29 presents the simulation results for a log slope of 100 mv/db (2 v/dec), covering 2-decade spans over several
rev. 0 e26e AD8362 sub-ranges, while figure 30 shows the results for a slope of 200 mv/db (4 v /dec), providing just a one-decade span. to accurately reposition the range (intercept) when very high slopes are used, a low output impedance dac can be used to provide v shift . figure 31 shows simulated results for a slope of 500 mv/db (10 v/dec) presuming this elaboration. in all cases, the fixed-pattern ripple in the log conformance remains unchanged, in db terms. residual fluctuations due to insufficient averaging (in low frequency applications) are like- wise unaffected in their equivalent decibel value, though greater in absolute voltage terms. rms input voltage shift ? db 100 v 1mv 10mv 10v output voltage ? v ?30 0 10 30 0 1 3 4 0.1v 1v 2 20 ?20 ?10 figure 29. illustrative results for slope of 100 mv/db rms input voltage shift ? db 100 v 1mv 10mv 10v output voltage ? v ?30 0 10 30 0 1 3 4 0.1v 1v 2 20 ?20 ?10 figure 30. illustrative results for slope of 200 mv/db rms input voltage shift ? db 100 v 1mv 10mv 10v output voltage ? v ?30 0 10 30 0 1 3 4 0.1v 1v 2 20 ?20 ?10 figure 31. illustrative results for slope of 10 v/dec AD8362 evaluation board the AD8362 evaluation board provides for a number of differ- ent operating modes, including many of those described above. the measurement mode is set up by positioning sw2 as shown in figure 32. it can be operated in controller modes by remov- ing lk1, flipping sw2 to its alternate position, and applying the set-point voltage to the v set connector. the internal voltage reference is used for the target voltage when sw1 is in the position shown in figure 32. this voltage may optionally be reduced via a voltage divider implemented with r4 and r5, with lk1 in place as shown and sw1 switched to its alternate position. alternatively, an external target voltage may be used if sw1 is switched to its alternate position lk1 removed and the external target voltage is applied to the v tgt connector. in measurement mode, the slope of the response at vout may be increased through the use of a voltage divider implemented with the appropriate resistors, as explained earlier in the data sheet, in positions r17 and r18. operation of the AD8362 is powered up with sw3 in the posi- tion shown in figure 32 and connector pwdn open. the part can be powered down either by connecting a logic hi to con- nector pwdn with sw3 in the position shown in figure 32, or by switching sw3 to its alternate position. balun transformer t1 may be removed and replaced either by two capacitors and an inductor, as shown in figure 17, or two 0 resistors (links, size 0402), one in series with capacitors c6 and c10, the other in series with c5, and a 100 resistor installed in position r16, to implement the circuit shown in figure 16.
rev. 0 AD8362 e27e 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 comm chpf decl inhi inlo decl pwdn comm a com vref vtgt vpos v out vset a com clpf AD8362 c6 100pf c5 100pf c7 1000pf c4 1000pf r15 0 r14 open c8 1000pf sw3 r16 open c10 1000pf rfin pdwn r13 10k r17 open sw2 c3 0.1 f c9 open r9 10k r5 10k r4 0 r6 0 r7 0 lk1 vref vtgt v out vset sw1 r10 0 r8 0 vpos r1 0 c2 100pf c1 0.1 f a gnd t1 figure 32. evaluation board schematic figure 33. component side metal of evaluation board figure 34. component side silkscreen of evalua- tion board
rev. 0 c02923e0e11/02(0) printed in u.s.a. e28e AD8362 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab table iii. evaluation board configuration options component function part number default value t1 etc1.6-4-2-3 c1 supply filtering/decoupling capacitor 0.1 f c2 supply filtering/decoupling capacitor 100 pf c3 output low-pass filter capacitor 0.1 f c9 output low-pass filter capacitor (normally omitted, not installed) c4, c7, c10 input bias-point decoupling capacitors 1000 pf c5, c6 input signal coupling capacitors 100 pf c8 input high-pass filter capacitor 1000 pf dut AD8362 AD8362aru r1, r4, r6, r7, r8, r10, r15 0 r5, r9, r13 optional pull-down resistors 10 k r16 (not installed, see text) 100 r17 slope adjustment (not installed, see text) (see text) ra (not installed, see text) 25 or 0 rb (not installed, see text) 33 rc (not installed, see text) 0 sw1 internal/external target voltage selector sw2 measurement mode/controller mode selector sw3 powerdown/enable or external power down selector

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